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List of TLP Application Notes

This informative section of our web site contains specific information for designer's who use TLP. We will be adding more information to this section periodically - please check back often.

Designer's may also find the material in our Technical Papers section useful.

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Preliminary Application Note 3

TLP TO HBM RISETIME CORRELATION

Reading from the Standard provided in "EOS/ESD-S5.1-1993", the pulse specification for HBM device testing has a 2 to 10 nanosecond risetime. This is a tremendous range of risetimes that could easily be tightened to provide closer correlation testing. With faster devices and protection structures, a closer tolerance on risetime will allow more precise test data correlation between different testers. The measurement of design structure protections or burnout is an ill-defined process now, and better knowledge of the test threats produced with HBM testers will assist the designers of protection structures.

This variation in risetimes has another effect that may cause different threats to the devices under test. With an HBM 15,000 volt pulse and a risetime of 10 ns, the rate of rise is about 1500 volts per ns, or 15 volts per 0.010 ns. Since the snapback occurs in approximately the first 15 volts, the rate of rise for TLP testing of the snapback region should be 0.010 ns to be equivalent to the HBM pulse. If possible, the exact risetime threat needs to be defined so that TLP testing will provide the most useful information for HBM protection.

Testing the snapback voltage can certainly be done with pulses that are slow enough to identify the maximum highest snapback voltage. To test the shape of the protection structure in the snapback area that simulates the actual HBM pulse, a much faster pulse must be used to equal the volts per nanosecond of a 15 kV HBM pulse with a 10 ns risetime.

Early in our design of TLP prototypes, we found that the amount of snapback on some devices was directly dependent on the test pulse risetime. Slow risetimes of 80 ns allowed the voltage to increase to its maximum level before snapback occurred. When the fastest (0.2 ns) TLP test pulse risetime was used, the voltage between snapback and voltage at holding current was reduced to a fraction of a volt. Similar voltage differences occur when the test pulse risetime is approximately 10 ns. Details of the effect over a range of different risetimes will be provided with exact waveforms with different device structures in later application notes.

Fast pulses can force the DUT into snapback before the voltage across the DUT reaches the level attained with slower pulses. This dI/dT effect can now be carefully studied with our risetime filter accessories. They have been specifically designed for use with the Model 4002 TLP test system and provide TLP test pulses smooth Gaussian risetimes from 0.2ns to 20.0 ns. Not being "device" experts, we cannot tell you what effect these different risetimes will have on your devices; but they are available with the Model 4002 system for your testing use.

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