Barth Electronics, Inc. has been designing state-of-the-art, fast-pulse, high-voltage measurement hardware for over 40 years. 









Barth Electronics, Inc.

Technical Papers

Some of the following papers are provided in pdf format. You will need to have Adobe Acrobat Reader installed on your computer to read these papers. To download the latest version of Adobe Acrobat Reader, click here.

Additional papers will be added soon. Please continue to check back periodically for the latest information on TLP.

Designer's will also find the information in our new Designer's Corner to be a useful reference on TLP.

What is TLP?
How to know when you've been zapped.
CE TLP Article March-April 2001.
2005 October IEEE Instrumentation and Measurements Recalibration.
2005 March IEEE Instrumentation and Measurements The Import.
2005 EOS-ESD Voltages before and after.
2004 March Journal of Electrostatics Real HBM and MM Wavef
2003 EOS-ESD Real HBM & MM - The dV-dT Threat
2002 EOS-ESD Correlation Considerations II - Real HBM to HB
2001 IEEE TLP Calibration
2001 EOS-ESD Correlation Real HBM to TLP
2000 ISTFA TLP Testing of the ESD Protection Structure
2000 EOS-ESD Importance of Standardizing CDM ESD Test Head
1999 EOS-ESD Issues Concerning CDM ESD Verification Modules
1999 EOS-ESD Developing a Transient Induced Latch Up Standard
1998 EOS-ESD Metrology and Methodology of System Level ESD
1998 EOS-ESD Investigation into Socketed CDM (SDM) Tester
1996 EOS-ESD Measurements of ESD HBM Events
1985 EOS-ESD TLP Techniques for Circuit Modeling


Developing a Transient Induced Latch-up Standard for Testing Integrated Circuits
by
M. Kelly, Leo G. Henry, Jon Barth, G. Weiss, M. Chaine, H.Geiser, D. Bonfert, T. Meuse, V. Gross, C. Hatchard, I. Morgan
Published by EOS/ESD Symposium Book 1999, Pgs. 178-189

The Importance of Standardizing CDM ESD Test Head Parameters to Obtain Data Correlation
by Leo G. Henry, Mark A. Kelly, Tom Diep, Jon Barth
Published in EOS/ESD Symposium Proceedings Book 2000, Paper 2A.2, Pgs 72-84

Investigation Into Socketed CDM (SDM) Tester Parasitics
by
M. Chaine, K. Verhaege, L. Avery, M. Kelly, H. Gieser, K. Bock, L.G. Henry, T. Meuse, T. Brodbeck, J. Barth
Published by EOS/ESD Symposium Book 1998, Pgs 301-310, Paper 4A.5

Issues Concerning CDM ESD Verification Modules, The Need to Move to Alumina
by Leo G. Henry, Mark Kelly, Tom Diep, Jon Barth
Published by EOS/ESD Symposium Book 1999, Pgs 203-211, Paper 3A.3

Metrology and Methodology of System Level ESD Testing
by Don Lin, D. Pommerenke, J. Barth, L.G. Henry, H. Hyatt, M. Hopkins, G. Senko, D. Smith
Published by EOS/ESD Symposium Book 1998, Pgs. 29-39, Paper 1B.3

Transmission Line Pulse Testing of the ESD Protection Structures of ICs - A Failure Analysts Perspective
by Leo G. Henry, ESD/TLP Consultant, Fremont, CA, USA; Jon Barth, John Richner, Barth Electronics Inc., Boulder City, NV, USA; Koen Verhaege, Sarnoff Corporation, Princeton, NJ, USA
ISTFA 2000: Book and CD-ROM Set, ASM International, Materials Park, OH 44073-0002, pgs. 203-213

TLP Calibration, Correlation, Standards, and New Techniques
by Jon E. Barth, Member, IEEE, Koen Verhaege, Leo G. Henry, Member, IEEE, and John Richner
IEEE Transactions on Electronics Packaging Manufacturing, VOL 24, No. 2, April, 2001

Correlation Considerations: Real HBM to TLP and HBM Testers
by Jon Barth, John Richner, Barth Electronics

Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena
by Timothy J. Maloney and Neeraj Khurana, Intel Corporation, Santa Clara, CA.
1985 EOS/ESD Symposium

Transmission-Line Pulse ESD Testing of ICs: A New Beginning
by Leo G. Henry, Jon Barth, Koen Verhaege, and John Richner
Compliance Engineering, March/April 2001

The SDM Test Method: Past, Present, and Future
by Michael Chaine, Jon Barth, Tilo Brodbeck, Leo G. Henry, Mark A. Kelly, and Tom Meuse
Compliance Engineering, September/October 2001



Barth Electronics, Inc.
1589 Foothill Drive, Boulder City, NV 89005
Phone: 702-293-1576 Fax: 702-293-7024
E-mail:
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